(1) Field of the Invention
This invention relates to a method of fabricating a non-volatile semiconductor memory cell, and more specifically to a memory cell comprised of an arrangement of a control gate and floating gates, allowing multiple data storage, on the same cell, to be realized.
(2) Description of the Prior Art
Numerous applications for non-volatile memory devices have been used in advanced semiconductor products. One type of non-volatile memory device, widely used in the semiconductor industry has been the erasable electrically programmable read only memory, (EEPROM), device. The most commonly used EEPROM is comprised of a double--gate cell, in which a floating gate, usually comprised of polysilicon, overlays a thin insulator layer, and also directly underlies a control gate, again usually comprised of polysilicon. Another insulator layer separates the control gate from the underlying floating gate. This type of configuration results in only single bit, or two levels of data storage. Attempts at fabricating non-volatile memory devices, possessing logic multiple storage functions have two approaches. One approach uses a multiple level storage scheme in which instead of only one threshold to define the store, high or low, multiple threshold voltages of the memory cell can be used, allowing the storage of multiple bits (01, 10, 11), in the same cell. However due to the constraint of the supply voltage, the multiple threshold voltage scheme operates with a reduced noise margin. This is not practical for low power, (low voltage), EEPROM devices. Another approach is to store more than one bit of information in the same cell, the multiple storage data scheme, however still maintaining one threshold voltage, for a the desired large noise margin. For example Kohda, et al, in U.S. Pat. No. 5,021,999, have described an EEPROM cell in which two bit data storage, on a single cell, is available. This is accomplished by using two floating gate shapes, lying on a thin insulator layer, and with a control gate shape, overlying the two floating gates shapes, separated from the floating gate shapes by another insulator layer. Although this non-volatile structure increases storage density, levels, several aspects of the structure remained non-optimized. For example in the Kohda, et al, invention, although the program, or write cycle, is achieved by properly biasing the control gate and drain region, ultimately resulting in electrons being injected into the floating gate, the erase cycle has to be performed using UV light. Under UV light the electrons trapped in the floating gate are dissipated into the substrate. In addition in the Kohda, et al, invention, the floating gate shapes have significant lateral dimensions, reducing the efficiency of the multiple storage schemes contribution to cell density.
This invention will describe the fabrication of an EEPROM cell, offering multiple storage capability. However unlike Kohda, et al, this invention will use Fowler--Nordheim injection, achieved using specific biasing configurations, to achieve the erase function of the device, thus avoiding the need for UV processing. In addition the floating gate structures will be obtained from creating spacer shapes, on the sidewalls of an insulator coated, control gate structure, thus more efficiently, reducing the cell area.